The semiconductor test device is a device which tests the operation of a device under test (hereinafter called DUT) by inputting signals of prescribed pattern data to the DUT, reading the output data of the DUT resulted from the input signals, and comparing the output data with the expected data.
Recently, as the transfer bit rate of the CPU, MPU, memories, etc. increases, it becomes necessary to compensate the transmission loss at connections between respective LSIs. Usually, the transmission line has integration characteristics, and thus, the high frequency component of a signal is lost. To cope with such a problem, a high frequency emphasizing circuit for compensating the transmission loss is often provided in an LSI as disclosed by Japanese Patent No. 3509258.
The LSI incorporating such a high frequency emphasizing circuit must be tested as to whether or not the high frequency emphasizing circuit operates correctly.